The invention relates to a ROM memory cell of the type mentioned in the preamble of Patent Claim 1. The invention furthermore relates to a ROM memory component, and to a method for reading from a ROM memory cell.
Semiconductor memories, that is to say semiconductor components comprising at least one memory cell, are used for storing information in digital systems. The semiconductor memories are subdivided into classes according to the type of information storage and the various possibilities for writing the information to the memory and reading it out again. If the memory retains the information even when the supply voltage is switched off, then this is referred to as a non-volatile memory or read-only memory, such as, for example, a ROM (Read Only Memory). The class of volatile memories includes static and dynamic memories, for example SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), which can be written to and read from freely after production. In contrast thereto, mask-programmed ROM memories generally cannot be written to after production.
A conventional ROM memory component comprises a multiplicity of ROM memory cells each containing a transistor. The individual transistors of the ROM memory component are typically embodied as MOS transistors (Metal Oxide Semiconductor) and arranged in matrix-type fashion in a memory cell array of the ROM memory component. In this case, the source terminal of the transistor is connected to an earth voltage, the drain terminal of said transistor is optionally connected to a bit line and the gate terminal of said transistor is connected to a word line. A ROM memory component comprising such memory cells is described in the German Patent Application DE 103 35 385 A1, which forms the generic type.
In the standby operating mode, an earth potential is applied to the source terminal and the gate terminal of such a ROM memory transistor, while the positive supply potential is applied to the drain terminal. However, such memory cell architectures have relatively high leakage currents, that is to say parasitic currents, in the standby operating mode. Said leakage currents are attributable to various causes: the leakage current IGate designates a parasitic current between the drain or source terminal and the gate terminal. The leakage current IJunc designates a parasitic current via the pn junction between the drain or source terminal and the substrate. The leakage current IOFF designates a parasitic current in the region of the channel of the transistor, that is to say between the latter's drain zone and source zone. These leakage currents are undesirable since, in the standby operating mode, in which the ROM memory cells are therefore not required, the latter nevertheless have a non-negligible current consumption which can rapidly exhaust the local power supply, particularly for mobile applications. For these reasons, consideration is increasingly being given to reducing the leakage currents in modern ROM memory cell architectures.
FIG. 1 shows the circuit diagram of a generally known leakage current optimized memory cell. FIG. 1a shows the associated signal-time diagrams.
FIG. 1 illustrates an individual memory transistor ST, the gate terminal G of which is connected to a word line WL, the drain terminal D of which is connected to a bit line BL and the source terminal S of which is connected to a supply line VL. A positive supply potential VDD is applied to the supply line VL and to the bit line BL in the standby operating mode illustrated. The potential VSS=0 volts is applied to the word line WL in the standby operating mode. Although the ROM memory cell architecture in FIG. 1 permits the leakage current IOFF to be completely suppressed, the leakage current IGate and IJunc is undesirably doubled by this memory cell architecture.
Modern memory technologies provide for increasing integration. In future memory generations produced using so-called deep-sub-micron technology, that is to say with feature sizes of 70 nm or less, the leakage current IGate, in particular, will increase greatly. This is due to the fact that with increasing integration the gate oxide becomes thinner and thinner, as a result of which the leakage current IGate becomes greater and greater on account of tunnel effects through the gate oxide.
A further problem inherent to the known memory cell architecture according to FIG. 1 arises when reading from the ROM memory cell. Prior to the read-out of the information contained in the memory cell, the source terminal S connected to the supply line VL is firstly discharged, for example to the potential 0 volts, in order to activate the memory transistor ST during read-out via the word line WL and thus via its gate terminal G. In this case, the voltage VGS dropped between the gate terminal G and the drain terminal D, after the discharge of the source terminal S, should ideally be equal to the potential of the bit line BL, so that VGS=VDD holds true. However, if the discharge of the source terminal S is not complete, for example in the case of a very high bit line capacitance, then the gate-source voltage VGS during read-out is rather VGS=VDD−VVSS, where VVSS denotes the potential still remaining at the source terminal S after the discharge. Consequently, the memory transistor ST cannot be activated rapidly enough, which entails a lower read-out speed of the ROM memory cell.